Microelectronic devices generally have a die (i.e., a chip) that includes integrated circuitry having a high density of very small components. In a typical process, a large number of dies are manufactured on a single wafer using many different processes that may be repeated at various stages (e.g., implanting, doping, photolithography, chemical vapor deposition, physical vapor deposition, plasma enhanced chemical vapor deposition, plating, planarizing, etching, etc.). The dies typically include an array of very small bond-pads electrically coupled to the integrated circuitry. The bond-pads are the external electrical contacts on the die through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry. The dies are then separated from one another (i.e., singulated) by backgrinding the wafer followed by dicing. After the dies have been singulated, they are typically “packaged” to couple the bond-pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines.
Conventional processes for packaging dies include electrically coupling the bond-pads on the dies to an array of pins, ball-pads, or other types of electrical terminals, and then encapsulating the dies to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact). In one application, the bond-pads are electrically connected to contacts on an interposer substrate that has an array of ball-pads. For example, FIG. 1 schematically illustrates a conventional packaged microelectronic device 2 including a microelectronic die 10, an interposer substrate 20 attached to the die 10, a plurality of wire-bonds 32 electrically coupling the die 10 to the substrate 20, a casing 50 protecting the die 10 from environmental factors, and a plurality of solder balls 60 attached to the substrate 20. The die 10 and interposer substrate 20 have a flat, planar configuration so that the solder balls 60 are aligned and positioned for attachment to an external device such as a printed circuit board.
Conventional memory dies 10 such as DRAM chips include an integrated circuit 12 with memory cells for retaining data. The data in each memory cell is based on a capacitor's ability to hold a charge. As a result, the die 10 must periodically refresh the data (i.e., recharge the capacitors) or the data will be lost. The refresh time of a die is related to the time that the weakest memory cell holds a charge. Refreshing the data in the memory cells requires internal resources that increase the power consumption of the die, reduce the speed at which the die operates, and/or increase the size of the die. As a result, it is desirable to increase the refresh time of memory dies.